// qs5_hdl.v  Pre-synthesis simulation command file

`timescale        1ns/1ns

// verilog source

`include "..\verilog\qs5_mix.v"

// test-fixture

`define memfile   ".\test.mem"      // execution memory image filename
`define chrfile   ".\test.chr"      // characters for host to send
`define outfile   ".\qs5_hdl.out"   // put output file in test directory

`include "..\verilog\qs5_ql08.tf"