// qs5_par.v  post synthesis, post place & route simulation command file

`timescale        1ns/1ns

// QuickLogic Cell Library

!LIB ..\chip\qlprim.v

// verilog netlist file after SpDE place & route

`include "..\chip\qs5_mix.vq"

// test-fixture

`define memfile   ".\test.mem"      // execution memory image filename
`define chrfile   ".\test.chr"      // characters for host to send
`define outfile   ".\qs5_par.out"   // put output file in test directory

`include "..\verilog\qs5_ql08.tf"

// timing delay values

module annotate();
initial
   $sdf_annotate("..\chip\qs5_mix.sdf",t.m);
endmodule